1. Field of the Invention
The present invention relates to sense amplifier circuits for memory devices, and more particular relates to sense amplifier circuits for static random access memory (SRAM) integrated circuit devices.
2. Description of the Related Art
FIG. 1 illustrates a block diagram for an SRAM memory device 100. A memory array 102 includes a plurality of word lines 105 (also frequently referred to as “row lines” or “rows”) and a plurality of complementary bit line pairs 110 (also frequently referred to as “column lines” or “columns”). One such word line 132 is shown, which is also labeled as WLx. One such complementary bit line pair 136, 134 is shown, which includes a true bit line 136 (also labeled as BLxT) and a complement bit line 134 (also labeled as BLxC). The memory array 102 includes a plurality of memory cells (such as memory cell 130) each coupled to an associated word line (such as word line 132) and coupled to an associated complementary bit line pair (such as bit line pair 136, 134).
A row decoder 104 receives and decodes a plurality M of row addresses 106 to generate the plurality 2M of word lines 105, one of which is selected and driven to an active level during a memory operation (e.g., a read or write), and the remaining word lines are unselected and driven or maintained at an inactive level. The word line 130 may be viewed as the selected word line, which is typically driven to an active level equal to the VDD voltage, while unselected word lines 105 are typically held at an inactive level equal to the ground reference voltage (i.e., typically “held at ground”).
A column decoder and multiplexer 112 receives and decodes a plurality N of column addresses 108 to select one or more of the plurality 2N of complementary bit line pairs 110, and couple the selected bit line pairs via interconnections 113 to a group of sense amplifiers 114. In a read operation, the respective output from each sense amplifier 114 is coupled via interconnections 116 to a respective one of a group of input/output circuits 118 to drive the respective inputs/outputs 120. In a write operation, data to be written is presented to the inputs/outputs 120, buffered by the input/output circuits 118 and conveyed to the sense amplifiers/write drivers 114, and coupled through the column decoder and multiplexer 112 to the one or more selected complementary bit line pairs 110.
A control circuit 122 serves to control the operation of the various components of the SRAM memory device 100 in its various modes of operation, such as a read mode, a write mode, and a standby mode, in response to one or more control signal inputs (not shown).
Referring now to FIG. 2, a common six-transistor CMOS memory cell 130, and a traditional sense amplifier 114 are shown for such a SRAM memory device 100. The memory cell 130 includes a pair of cross-coupled inverters, and a pair of passgate transistors (also known as “access transistors”). One such inverter is formed by P-channel transistor 144 and N-channel transistor 146, and the other inverter is formed by P-channel transistor 145 and N-channel transistor 147. The two cross-coupled nodes 141, 143 are coupled respectively to bit lines 136, 134 by respective access transistors 140, 142 whose gate terminals are coupled to the word line 132.
If selected in a read mode of operation, the bit line pair 136, 134 is coupled through the column multiplexer 112 to nodes 152, 154 of sense amplifier 114. The three P-channel transistors 164, 165, 166 together form an equilibration circuit to equilibrate the internal sense amplifier nodes 154, 156 and to precharge both such nodes to VDD when enabled by an active-low precharge signal PCX conveyed on node 168.
Transistors 156, 158, 160, 162, 163 together form a latching differential amplifier which is enabled by asserting an active-high enable signal SAEN on node 172. Since the internal sense amplifier nodes 152, 154 are equilibrated to VDD between sensing operations, when sensing begins both P-channel transistors 156, 158 are turned off. The two N-channel transistors 160, 162 form a differential pair, and transistor 163 serves to provide the tail current for transistors 160, 162. The sense amplifier node 152, 154 having the lower voltage (as a result of the data state of memory cell 130) is driven to ground, and the other sense amplifier node 152, 154 having the higher voltage is driven to (or maintained at) VDD.
When bit lines are precharged to a relatively “high” VDD voltage, a selected memory cell may experience a read stability failure due to the voltage divider formed by the passgate transistor and the inverter pull-down transistor in the bitcell. For example, if a logic “1” is stored in the memory cell 130, internal bitcell node 141 is high (VDD) and internal bitcell node 143 is low (ground). Both bit lines 136, 134 are precharged to VDD before the read operation begins. When the selected word line 132 is driven to VDD, transistors 142 and 147 form a voltage divider that tends to raise the voltage of internal node 143 from ground to a voltage higher than ground, since the gate terminals of both transistors 142 and 147 are at VDD, the drain terminal of transistor 142 is at VDD, and the source terminal of transistor 147 is at ground. Node 143 may easily rise in voltage to a significant fraction of the VDD voltage, depending upon the ratio of transistors 142 and 147. If the voltage of node 143 is raised high enough, it may cause instability in the cross-coupled latch and cause the memory cell 130 to flip states, thereby causing an error in the memory array.
However, if bit lines are precharged to a voltage lower than VDD, the common-mode voltages of the true and complement sense amplifier nodes (which largely follows the common-mode voltage of the selected bit line pair) may be too low to “steer” the N-channel differential amplifier (i.e., transistors 160, 162, and 163) when enabled by the SAEN signal, or at best may cause the N-channel differential amplifier to function very slowly. In addition, a short-circuit current (i.e., “crowbar” current) may flow through the sense amplifier output inverters as a result of the non-rail input voltage of such inverters. In this context, VDD is the voltage to which the selected word line is driven, and which is used to power the memory cells in the array.
As process technology improvement has steadily reduced the critical line widths and feature sizes, the VDD operating window has become smaller, and proper circuit operation has become more difficult to obtain.